HD6433308 Datasheet, PDF (178/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

øØ
External reset
input (TMRI)
Internal clear
pulse
TCNT
N–1
N
H’00
Figure 7-9. Timing of External Reset
7.3.4 Setting of TCSR Overflow Flag
(1) Setting of TCSR Overflow Flag (OVF): The overflow flag (OVF) is set to “1” when the
timer count overflows (changes from H’FF to H’00). Figure 7-10 shows the timing of this
operation.
Øø
TCNT
H’FF
H’00
Internal overflow
signal
OVF
Figure 7-10. Setting of Overflow Flag (OVF)
(2) Timing of TCSR Overflow Flag (OVF) Clearing: The overflow flag (OVF) is cleared when
the CPU writes a “0” in this bit.
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