HD6433308 Datasheet, PDF (8/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Section 10. A/D Converter .....................................................................................................207
10.1 Overview............................................................................................................................... 207
10.1.1 Features.................................................................................................................... 207
10.1.2 Block Diagram......................................................................................................... 208
10.1.3 Input Pins................................................................................................................. 209
10.1.4 Register Configuration ............................................................................................ 209
10.2 Register Descriptions............................................................................................................ 210
10.2.1 A/D Data Registers (ADDR) – H'FFE0 to H'FFE6................................................. 210
10.2.2 A/D Control/Status Register (ADCSR) – H'FFE8 .................................................. 210
10.2.3 A/D Control Register (ADCR) – H'FFEA............................................................... 213
10.3 Operation .............................................................................................................................. 213
10.3.1 Single Mode (SCAN = 0) ........................................................................................ 214
10.3.2 Scan Mode (SCAN = 1) .......................................................................................... 217
10.3.3 Input Sampling Time and A/D Conversion Time.................................................... 220
10.3.4 External Trigger Input Timing................................................................................. 222
10.4 Interrupts............................................................................................................................... 223
Section 11. Dual-Port RAM (Parallel Communication Interface) ...............................225
11.1 Overview............................................................................................................................... 225
11.1.1 Features.................................................................................................................... 225
11.1.2 Block Diagram......................................................................................................... 226
11.1.3 Input and Output Pins .............................................................................................. 227
11.1.4 Register Configuration ............................................................................................ 227
11.2 Register Descriptions............................................................................................................ 228
11.2.1 Dual Port RAM Enable Bit (DPME)....................................................................... 228
11.2.2 Parallel Communication Data Register 0 (PCDR0) – H'FFF1................................ 230
11.2.3 Parallel Communication Data Registers 1 to 14 –
H'FFF2 (PCDR1) to H'FFFF (PCDR1-14).............................................................. 231
11.2.4 Parallel Communication Control/Status Register (PCCSR) – H'FFF0 ................... 231
11.3 Usage .................................................................................................................................... 234
11.3.1 Data Transfer from Master CPU to H8/300 CPU.................................................... 234
11.3.2 Data Transfer from H8/300 CPU to Master CPU.................................................... 235
11.4 Master-Slave Interconnections ............................................................................................. 237
Section 12. RAM....................................................................................................................... 239
12.1 Overview............................................................................................................................... 239
12.2 Block Diagram...................................................................................................................... 239
12.3 RAM Enable Bit (RAME) .................................................................................................... 239
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