HD6433308 Datasheet, PDF (249/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Section 12. RAM
12.1 Overview
The H8/330 includes 512 bytes of on-chip static RAM, connected to the CPU by a 16-bit data bus.
Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data
transfer and instruction execution.
The on-chip RAM is assigned to addresses H’FD80 to H’FF7F in the chip’s address space. The
RAME bit in the system control register (SYSCR) can enable or disable the on-chip RAM,
permitting these addresses to be allocated to external memory instead, if so desired.
12.2 Block Diagram
Figure 12-1 is a block diagram of the on-chip RAM.
Address
H'FD80
H'FD82
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FD80
H'FD82
H'FD81
H'FD83
H'FF7E
On-chip RAM
H'FF7E
H'FF7F
Even address Odd address
Figure 12-1. Block Diagram of On-Chip RAM
12.3 RAM Enable Bit (RAME)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control
register (SYSCR). Table 12-1 lists information about the system control register.
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