HD6433308 Datasheet, PDF (320/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

TCR—Timer Control Register
H’FF96
FRT
Bit
7
6
IEDGA IEDGB
Initial value 0
0
Read/Write R/W R/W
5
IEDGC
0
R/W
4
3
2
IEDGD BUFEA BUFEB
0
0
0
R/W R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock Select
0 0 Internal clock source: Ø/2
0 1 Internal clock source: Ø/8
1 0 Internal clock source: Ø/32
1 1 External clock source: counted on rising edge
Buffer Enable B
0 ICRD is used for input capture D.
1 ICRD is buffer register for input capture B.
Buffer Enable A
0 ICRC is used for input capture C.
1 ICRC is buffer register for input capture A.
Input Edge Select D
0 Falling edge of FTID is valid.
1 Rising edge of FTID is valid.
Input Edge Select C
0 Falling edge of FTIC is valid.
1 Rising edge of FTIC is valid.
Input Edge Select B
0 Falling edge of FTIB is valid.
1 Rising edge of FTIB is valid.
Input Edge Select A
0 Falling edge of FTIA is valid.
1 Rising edge of FTIA is valid.
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