HD6433308 Datasheet, PDF (191/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

(1) Positive Logic (OS = “0”)
Œ When (OE = “0”) – (a) in Figure 8-3: The timer count is held at H’00 and PWM output is
inhibited. (Pin 46 (for PW0) or pin 47 (for PW1)is used for port 4 input/output, and its state
depends on the corresponding port 4 data register and data direction register.) Any value (such as
N in Figure 8-3) written in the DTR becomes valid immediately.
y When (OE = “1”)
i) The timer counter begins incrementing. The PWM output goes High when TCNT changes
from H’00 to H’01, unless DTR = H’00. [(b) in Figure 8-3]
ii) When the count passes the DTR value, the PWM output goes Low. [(c) in Figure 8-3]
iii) If the DTR value is changed (by writing the data “M” in Figure 8-3), the new value
becomes valid after the timer count changes from H’F9 to H’00. [(d) in Figure 8-3]
(2) Negative Logic (OS = “1”) – (e) in Figure 8-3: The operation is the same except that High
and Low are reversed in the PWM output . [(e) in Figure 8-3]
8.4 Application Notes
Some notes on the use of the PWM timer module are given below.
(1) Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to “1.”
(2) If the DTR value is H’00, the duty factor is 0% and PWM output remains constant at “0.” If
the DTR value is H’FA to H’FF, the duty factor is 100% and PWM output remains constant at
“1.”
(For positive logic, “0” is Low and “1” is High. For negative logic, “0” is High and “1” is
Low.)
(3) When the DTR is read, the currently valid value is obtained. Due to the double buffering, this
may not be the value most recently written.
(4) Software should never write to a PWM timer counter. The write function is for test purposes
only and may have unintended effects in normal operation.
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