HD6433308 Datasheet, PDF (302/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Appendix B. Instruction Set List (cont.)
Mnemonic
BIOR #xx:3,@Rd
BIOR #xx:3, @aa:8
BXOR #xx:3,Rd
BXOR #xx:3,@Rd
BXOR #xx:3, @aa:8
BIXOR #xx:3,Rd
BIXOR #xx:3,@Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
JMP @Rn
JMP @aa:16
JMP @@aa:8
BSR d:8
Operation
Branching
condition
B C∨(#xx:3 of @Rd16) → C
B C∨(#xx:3 of @aa:8) → C
B C⊕(#xx:3 of Rd8) → C
B C⊕(#xx:3 of @Rd16) → C
B C⊕(#xx:3 of @aa:8) → C
B C⊕(#xx:3 of Rd8) → C
B C⊕(#xx:3 of @Rd16) → C
B C⊕(#xx:3 of @aa:8) → C
– PC ← PC+d:8
– PC ← PC+2
– if condition C ∨ Z = 0
– is true then C ∨ Z = 1
– PC ← PC+d:8 C = 0
– else next;
C=1
–
Z=0
–
Z=1
–
V=0
–
V=1
–
N=0
–
N=1
–
N⊕V = 0
–
N⊕V = 1
–
Z ∨ (N⊕V) = 0
–
Z ∨ (N⊕V) = 1
– PC ← Rn16
– PC ← aa:16
– PC ← @aa:8
– SP–2 → SP
PC → @SP
PC ← PC+d:8
Addressing mode/
instruction length
Condition code
4
2
4
2
4
2
I H N ZV C
– –– – – ◊ 6
4
– –– – – ◊ 6
– –– – – ◊ 2
– –– – – ◊ 6
4
– –– – – ◊ 6
– –– – – ◊ 2
– –– – – ◊ 6
4
– –– – – ◊ 6
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
2
– –– – – – 4
– –– – – – 4
4
– –– – – – 6
2 – –– – – – 8
2
– –– – – – 6
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