HD6433308 Datasheet, PDF (163/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Write cycle: CPU write to lower byte of FRC
T1
T2
T3
Ø
Internal address bus
Internal write signal
FRC address
FRC clock pulse
FRC
N
M
Write data
Figure 6-22. FRC Write-Increment Contention
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and
the compare-match signal is inhibited.
Figure 6-22
Figure 6-23 shows this type of contention.
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