HD6433308 Datasheet, PDF (284/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 17-6. Timing Conditions of On-Chip Supporting Modules (cont.)
Conditions: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Dual-
port
RAM
read
cycle
Dual-
port
RAM
write
cycle
Measurement 6MHz
Item
Symbol conditions min max
Address
tDAA Fig. 17-20 – 150
access time
CS access
tDACS Fig. 17-20
– 130
time
OE output
tDOE Fig. 17-20 – 70
delay time
CS output
tDCHZ Fig. 17-20
– 50
floating time
OE output
tDOHZ Fig. 17-20
– 50
floating time
Output data
tDOH Fig. 17-20
0–
hold time
Chip select time tDCW Fig. 17-21 100 –
Address valid tDAW Fig. 17-21 100 –
time
Address setup tDAS Fig. 17-21 20 –
time
Write pulse
tDWP Fig. 17-21 90 –
width
Address hold tDWR Fig. 17-21 20 –
time
Input data
tDDW Fig. 17-21 60 –
setup time
Input data
tDDH Fig. 17-21 15 –
hold time
8MHz
min max
– 150
– 130
– 70
– 50
– 50
0–
100 –
100 –
20 –
90 –
20 –
60 –
15 –
10MHz
min max Unit
– 150 ns
– 130 ns
– 70 ns
– 50 ns
– 50 ns
0 – ns
100 – ns
100 – ns
20 – ns
90 – ns
20 – ns
60 – ns
15 – ns
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