HD6433308 Datasheet, PDF (333/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

TCSR—Timer Control/Status Register
H’FFC9
TMR0
Bit
7
6
5
4
3
2
1
0
CMFB CMFA OVF
— OS3*² OS2*² OS1*² OS0*²
Initial value 0
0
0
1
0
0
0
0
Read/Write R/(W)*¹ R/(W)*¹ R/(W)*¹ — R/W R/W R/W R/W
Output Select
0 0 No change on compare-match A.
0 1 Output “0” on compare-match A.
1 0 Output “1” on compare-match A.
1 1 Invert (toggle) output on compare-match A.
Output Select
0 0 No change on compare-match B.
0 1 Output “0” on compare-match B.
1 0 Output “1” on compare-match B.
1 1 Invert (toggle) output on compare-match B.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when TCNT changes from H’FF to H’00.
Compare-Match Flag A
0 Cleared when CPU reads CMFA = “1,” then writes “0” in CMFA.
1 Set when TCNT = TCORA.
Compare-Match Flag B
0 Cleared from when CPU reads CMFB = “1,” then writes “0” in CMFB.
1 Set when TCNT = TCORB.
*¹ Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
*² When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
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