HD6433308 Datasheet, PDF (156/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

6.4.2 Output Compare Timing
(1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags
are set to “1” by an internal compare-match signal generated when the FRC value matches the
OCRA or OCRB value. This compare-match signal is generated at the last state in which the two
values match, just before the FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 6-8 shows the timing of the setting of the output
compare flags.
Ø
FRC
N
N+1
OCRA or OCRB
N
Internal compare-
match signal
OCFA or OCFB
Figure 6-8. Setting of Output Compare Flags
(2) Timing of Output Compare Flag (OCFA or OCFB) Clearing: The output compare flag
OCFA or OCFB is cleared when the CPU writes a “0” in this bit.
Write cycle: CPU writes "0" in OCFA or OCFB
T1
T2
T3
Ø
OCFA or OCFB
Figure 6-9. Clearing of Output Compare Flag
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