HD6433308 Datasheet, PDF (157/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

(3) Output Timing: When a compare-match occurs, the logic level selected by the output level
bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 6-
10 shows the timing of this operation for compare-match A.
Ø
FRC
N
N+1
N
N+1
OCRA
N
Internal compare-
match A signal
OLVLA
N
Clear *
FTOA
* Cleared by software
Figure 6-10. Timing of Output Compare A
(4) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared when
compare-match A occurs. Figure 6-11 shows the timing of this operation.
Figure 6-10
Ø
Internal compare-
match A signal
FRC
N
H'0000
Figure 6-11. Clearing of FRC by Compare-Match A
6.4.3 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 6-12 shows the usual input capture timing when the rising edge is
selected (IEDGx = “1”).
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