HD6433308 Datasheet, PDF (179/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

When cycle: CPU writes "0" in OVF
T1
T2
T3
Ø
OVF
Figure 7-11. Clearing of Overflow Flag
7.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 7-3 lists information about these interrupts.
Table 7-3. 8-Bit Timer Interrupts
Interrupt
CMIA
CMIB
OVI
Description
Requested when CMFA and CMIEA are set
Requested when CMFB and CMIEB are set
Requested when OVF and OVIE are set
Priority
High
Low
7.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor.
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to “0” and CCLR0 is set to “1” so that the timer counter is
cleared when its value matches the constant in TCORA.
(2) In the TCSR, bits OS3 to OS0 are set to “0110,” causing the output to change to “1” on
compare-match A and to “0” on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
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