HD6433308 Datasheet, PDF (60/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Before Execution of BSET Instruction
Input/output
Pin state
DDR
DR
Pull-up Mos
P47
Input
Low
0
1
On
P46
Input
High
0
0
Off
P45 P44 P43 P42 P41 P40
Output Output Output Output Output Output
Low Low Low Low Low Low
1
1
1
1
1
1
0
0
0
0
0
0
Off Off Off Off Off Off
Execution of BSET Instruction
BSET.B #0, @PORT4
;set bit 0 in data register
After Execution of BSET Instruction
Input/output
Pin state
DDR
DR
Pull-up
P47
Input
Low
0
0
Off
P46
Input
High
0
1
On
P45 P44 P43 P42 P41 P40
Output Output Output Output Output Output
Low Low Low Low Low High
1
1
1
1
1
1
0
0
0
0
0
1
Off Off Off Off Off Off
Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P47 and
P46 are input pins, the CPU reads the level of these pins directly, not the value in the data register.
It reads P47 as Low ("0") and P46 as High ("1").
Since P45 to P40 are output pins, for these pins the CPU reads the value in the data register ("0").
The CPU therefore reads the value of port 4 as H'40, although the actual value in P4DR is H'80.
Next the CPU sets bit 0 of the read data to "1," changing the value to H'41.
Finally, the CPU writes this value (H'41) back to P4DR to complete the BSET instruction.
As a result, bit P40 is set to "1," switching pin P40 to High output. In addition, bits P47 and P46 are
both modified, changing the on/off settings of the MOS pull-up transistors of pins P47 and P46.
Programming Solution: The switching of the pull-ups for P47 and P46 in example 2 can be
avoided by reserving a byte in RAM as a temporary register for P4DR and using it as follows.
RAM0 is a symbol for the user-selected address of the temporary register.
44