HD6433308 Datasheet, PDF (153/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

• Register Read
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte
is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
(As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes
directly, without using TEMP.)
Programs that access these registers should normally use word access. Equivalently, they may
access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be
transferred correctly if the bytes are accessed in reverse order, if only one byte is accessed, or if the
upper and lower bytes are accessed separately and another register is accessed in between, altering
the value in TEMP.
Coding Examples
To write the contents of general register R0 to OCRA:
To transfer the contents of ICRA to general register R0:
MOV.W R0, @OCRA
MOV.W @ICRA, R0
Figure 6-4 shows the data flow when the FRC is accessed. The other registers are accessed in the
same way.
(1) Upper byte write
CPU writes
data H’AA
Bus interface
Module data bus
TEMP
[H’AA]
(2) Lower byte write
FRC H
[]
FRC L
[]
CPU writes
data H’55
Bus interface
Module data bus
TEMP
[H’AA]
FRC H
[H’AA]
FRC L
[H’55]
Figure 6-4 (a). Write Access to FRC (When CPU Writes H’AA55)
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