HD6433308 Datasheet, PDF (225/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

10.2.3 A/D Control Register (ADCR) – H’FFEA
Bit
7
6
5
4
3
2
1
0
TRGE —
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W —
—
—
—
—
—
—
The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the
A/D external trigger signal.
The ADCR is initialized to H’7F at a reset and in the standby modes.
Bit 7 – Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal to set
the ADST bit and start A/D conversion.
Bit 7
TRGE
0
1
Description
A/D external trigger is disabled. ADTRG does not set
the ADST bit.
A/D external trigger is enabled. ADTRG sets the ADST bit.
(The ADST bit can also be set by software.)
(Initial value)
Bits 6 to 0 – Reserved: These bits cannot be modified and are always read as “1.”
10.3 Operation
The A/D converter performs 8 successive approximations to obtain a result ranging from H’00
(corresponding to AVSS) to H’FF (corresponding to AVCC). Figure 10-2 shows the response of the
A/D converter.
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