HD6433308 Datasheet, PDF (187/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

The PWM timer counters can be read and written, but the write function is for test purposes only.
Application software should never write to a PWM timer counter, because this may have
unpredictable effects.
The PWM timer counters are initialized to H’00 at a reset and in the standby modes, and when the
OE bit is cleared to “0.”
8.2.2 Duty Register (DTR) – H’FFA1 (PWM0), H’FFA5 (PWM1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
The duty registers (DTR) are 8-bit readable/writable registers that specify the duty factor of the
output pulse. Any duty factor from 0 to 100% can be selected, with a resolution of 1/250. Writing
0 (H’00) in a DTR gives a 0% duty factor; writing 125 (H’7D) gives a 50% duty factor; writing 250
(H’FA) gives a 100% duty factor.
The timer count is continually compared with the DTR contents. If the DTR value is not 0, when
the count increments from H’00 to H’01 the PWM output signal is set to “1.” When the count
increments past the DTR value, the PWM output returns to “0.” If the DTR value is 0 (duty factor
0%), the PWM output remains constant at “0.”
The DTRs are double-buffered. A new value written in a DTR while the timer counter is running
does not become valid until after the count changes from H’F9 to H’00. When the timer counter is
stopped (while the OE bit is “0”), new values become valid as soon as written. When a DTR is
read, the value read is the currently valid value.
The DTRs are initialized to H’FF at a reset and in the standby modes.
8.2.3 Timer Control Register (TCR) – H’FFA0 (PWM0), H’FFA4 (PWM1)
Bit
7
6
5
4
3
2
1
0
OE
OS
—
—
— CKS2 CKS1 CKS0
Initial value
0
0
1
1
1
0
0
0
Read/Write
R/W R/W
—
—
—
R/W R/W R/W
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