HD6433308 Datasheet, PDF (89/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Figure 4-7 shows an example of damage caused when the stack pointer contains an odd address.
SP-4
SP-3
SP-2
SP-1
SP(R7)
Stack area
SP(R7)
SP+1
SP+2
SP+3
SP+4
CCR
CCR *
PC (upper byte)
PC (lower byte)
Even address
Before interrupt
is accepted
Pushed onto stack
PC : Program counter
CCR : Condition code register
SP : Stack pointer
After interrupt
is accepted
* : Ignored on return.
Notes: 1. The PC contains the address of the first instruction
executed after return.
2. Registers must be saved and restored by word
access at an even address.
Figure 4-6. Usage of Stack in Interrupt Handling
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