HD6433308 Datasheet, PDF (267/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

The NMI edge bit (NMIEG) in the system control register is originally cleared to "0," selecting the
falling edge. When NMI goes Low, the NMI interrupt handling routine sets NMIEG to "1," sets
SSBY to "1" (selecting the rising edge), then executes the SLEEP instruction. The H8/330 enters
the software standby mode. It recovers from the software standby mode on the next rising edge of
NMI.
Clock
generator
Ø
NMI
NMIEG
SSBY
Settling time
NMI interrupt handler
NMIEG = "1"
SSBY = "1"
Software standby mode
(power-down state)
SLEEP
NMI interrupt handler
Figure 14-1. Software Standby Mode (when) NMI Timing
14.4.4 Application Notes
(1) The I/O ports retain their current states in the software standby mode. If a port is in the High
output state, the current dissipation caused by the High output current is not reduced.
(2) If the software standby mode is entered under either condition x or condition  below, current
dissipation is greater than in normal standby mode.
x In single-chip mode (mode 3): if software standby mode is entered by executing an
instruction stored in on-chip ROM, after even one instruction not stored in on-chip ROM
has been fetched (e.g. from on-chip RAM).
 In expanded mode with on-chip ROM enabled (mode 2): if software standby mode is
entered by executing an instruction stored in on-chip ROM, after even one instruction not
stored in on-chip ROM has been fetched (e.g. from external memory or on-chip RAM).
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