HD6433308 Datasheet, PDF (232/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Note: If the ADST bit is cleared to "0" when two or more channels are selected in the scan mode,
incorrect values may be left in the A/D data registers.
For this reason, in the scan mode the A/D data registers should be read while the ADST bit is still
set to "1."
Example: The following coding example sets up a four-channel A/D scan, and shows the first part
of an ADI interrupt handler for reading the converted data. Note that the data are read before the
ADST bit is cleared.
MOV.B #5B
MOV.B R0L
BSET #5
, R0L
, @ADCSR ; Four-channel scan mode
, @ADCSR ; Start conversion (set ADST)
(Conversion of four channels)
ADI:
MOV.B
MOV.B
MOV.B
MOV.B
BCLR
BCLR
@ADDRA
@ADDRB
@ADDRC
@ADDRD
#5
#7
, R1
; Read ADDRA
, R2
; Read ADDRB
, R3
; Read ADDRC
, R4
; Read ADDRD
, @ADCSR ; Clear ADST
, @ADCSR ; Clear ADF
(It is not necessary to clear the ADST bit in order to read ADDRA to ADDRD.)
10.3.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time tD after the ADST bit is set to "1." The sampling process lasts for a time tSPL. The actual A/D
conversion begins after sampling is completed. Figure 10-5 shows the timing of these steps. Table
10-4 (a) lists the conversion times for the single mode. Table 10-4 (b) lists the conversion times for
the scan mode.
The total conversion time (tCONV) includes tD and tSPL. The purpose of tD is to synchronize the
ADCSR write time with the A/D conversion process, so the length of tD is variable. The total
conversion time therefore varies within the minimum to maximum ranges indicated in table 10-4
(a) and (b).
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