HD6433308 Datasheet, PDF (145/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 5
ICICE
0
1
Description
Input capture interrupt request C (ICIC) is disabled.
Input capture interrupt request C (ICIC) is enabled.
(Initial value)
Bit 4 – Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register
(TCSR) is set to “1.”
Bit 4
ICIDE
0
1
Description
Input capture interrupt request D (ICID) is disabled.
Input capture interrupt request D (ICID) is enabled.
(Initial value)
Bit 3 – Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control
register (TCSR) is set to “1.”
Bit 3
OCIAE
0
1
Description
Output compare interrupt request A (OCIA) is disabled.
Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 2 – Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control
register (TCSR) is set to “1.”
Bit 2
OCIBE
0
1
Description
Output compare interrupt request B (OCIB) is disabled.
Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 1 – Timer overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
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