HD6433308 Datasheet, PDF (75/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

4.1 Reset
A reset has the highest exception-handling priority. When the RES pin goes Low, all current
processing by the CPU and on-chip supporting modules halts. When RES returns from Low to
High, the following hardware reset sequence is executed.
(1) The value at the mode pins (MD1 and MD0) is latched in bits MDS1 and MDS0 of the mode
register (MDCR).
(2) In the condition code register (CCR), the I bit is set to “1” to mask interrupts.
(3) The registers of the I/O ports and on-chip supporting modules are initialized.
(4) The CPU loads the program counter with the first word in the vector table (stored at
addresses H’0000 and H’0001) and starts program execution.
A reset does not initialize the general registers or on-chip RAM.
All interrupts, including NMI, are disabled immediately after a reset. The first program instruction,
located at the address specified at the top of the vector table, is therefore always executed. This
instruction should be a MOV.W instruction initializing the stack pointer (R7). After execution of
this instruction, the NMI interrupt is enabled. Other interrupts remain disabled until their enable
bits are set to “1” and the interrupt mask is cleared.
To ensure correct resetting, at power-on the RES pin should be held Low for at least 20ms. In a
reset during operation, the RES pin should be held Low for at least 10 system clock periods. The
RES pin should also be held Low when power is switched off.
Figure 4-1 indicates the timing of the reset sequence when the vector table and reset routine are
located in on-chip ROM. Figure 4-2 indicates the timing when they are in off-chip memory.
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