HD6433308 Datasheet, PDF (162/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

6.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timers.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 6-21 shows this type of contention.
Write cycle: CPU write to lower byte of FRC
T1
T2
T3
Ø
Internal address bus
Internal write signal
FRC address
FRC clear signal
FRC
N
H'0000
Figure 6-21. FRC Write-Clear Contention
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3 state of a write cycle to the lower byte of the free-runni^Fnⁱg^guc^ro^eu⁶n^-t²e¹r, the write takes
priority and the FRC is not incremented.
Figure 6-22 shows this type of contention.
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