MC68HC708MP16 Datasheet, PDF (99/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
7.7.2 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break
caused an exit from wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R5
R
Write:
R
R
R
Note⁽¹⁾
R
Reset:
0
R = Reserved for factory test
NOTE 1. Writing a logic 0 clears SBSW.
Figure 7-15. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear SBSW by writing a logic 0 to
it. Reset clears SBSW.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit
clears it.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
99