MC68HC708MP16 Datasheet, PDF (116/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
8.6 CGM Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL) (See 8.6.1 PLL Control Register.)
• PLL bandwidth control register (PBWC) (See 8.6.2 PLL
Bandwidth Control Register.)
• PLL programming register (PPG) ((See 8.6.3 PLL Programming
Register.)
Figure 8-4 is a summary of the CGM registers.
PCTL
$FE0B
Read:
Write:
PBWC
$FE0C
Read:
Write:
PPG
$FE0D
Read:
Write:
Bit 7
PLLIE
Bit 7
AUTO
Bit 7
MUL7
6
5
4
PLLF
PLLON BCS
6
5
4
LOCK
ACQ
XLD
6
MUL6
5
MUL5
4
MUL4
3
1
3
0
3
VRS7
2
1
2
0
2
VRS6
1
1
1
0
1
VRS5
Bit 0
1
Bit 0
0
Bit 0
VRS4
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-4. CGM I/O Register Summary
Technical Data
116
Clock Generator Module (CGM)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor