MC68HC708MP16 Datasheet, PDF (128/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
The K factor in the equations is derived from internal PLL parameters.
K_ACQ is the K factor when the PLL is configured in acquisition mode, and
K_TRK is the K factor when the PLL is configured in tracking mode. (See
8.4.2.2 Acquisition and Tracking Modes.)
t_ACQ
=


V--f--_{R-D-D-D--V-A-}


-K----_A^8--_C---_Q-_
t_AL
=


V--f--_{R-D-D--D-V-A-}


-K----4_T--_R---_K-_
t_LOCK = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See 8.4.2.3
Manual and Automatic PLL Bandwidth Modes.) A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆_TRK, before exiting acquisition mode. A
certain number of clock cycles, n_TRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, ∆_LOCK. Therefore, the
acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV, and the
acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t_LOCK as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_LOCK before selecting the PLL clock (see 8.4.3 Base Clock Selector
Circuit) because the factors described in 8.10.2 Parametric Influences
on Reaction Time may slow the lock time considerably.
Technical Data
128
Clock Generator Module (CGM)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor