MC68HC708MP16 Datasheet, PDF (113/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
zero. This value would set up a condition inconsistent with the operation
of the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
8.4.4 CGM External Connections
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 8-3. Figure 8-3 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X₁
• Fixed capacitor, C₁
• Tuning capacitor, C₂ (can also be a fixed capacitor)
• Feedback resistor, R_B
• Series resistor, R_S (optional)
The series resistor (R_S) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 8-3 also shows the external components for the PLL:
• Bypass capacitor, C_BYP
• Filter capacitor, C_F
Routing should be done with great care to minimize signal cross talk and
noise. (See 8.10 Acquisition/Lock Time Specifications for routing
information and more information on the filter capacitor’s value and its
effects on PLL performance.)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
113