MC68HC708MP16 Datasheet, PDF (277/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
13.14.1 SPI Control Register
The SPI control register does the following:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
• Enables the SPI module
Address: $001B
Bit 7
6
5
4
3
2
1
Read:
SPRIE
Write:
DMAS
SPMSTR CPOL
CPHA SPWOM SPE
Reset: 0
0
1
0
1
0
0
= Unimplemented
Figure 13-13. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests
0 = SPRF CPU interrupt requests
DMAS —DMA Select Bit
This read-only bit has no effect on this version of the SPI. This bit
always reads as a 0.
0 = SPRF DMA and SPTE DMA service requests disabled
(SPRF CPU and SPTE CPU interrupt requests enabled)
SPMSTR — SPI Master Bit
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
277