MC68HC708MP16 Datasheet, PDF (239/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
The minimum TCLK pulse width, TCLK_LMIN or TCLK_HMIN, is:
------------------1-------------------
bus frequency
+
t_SU
The maximum TCLK frequency is:
bus frequency ÷ 2
PTE3/TCLKB is available as a general-purpose I/O pin when not used
as the TIMB clock input. When the PTE3/TCLKB pin is the TIMB clock
input, it is an input regardless of the state of the DDRE3 bit in data
direction register E.
12.8.2 TIMB Channel I/O Pins (PTE4/TCH0B:PTE7/TCH3B)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE4/TCH0B and PTE6/TCH2B
can be configured as buffered output compare or buffered PWM pins.
12.9 I/O Registers
The following I/O registers control and monitor operation of the TIMB:
• TIMB status and control register (TBSC)
• TIMB control registers (TBCNTH:TBCNTL)
• TIMB counter modulo registers (TBMODH:TBMODL)
• TIMB channel status and control registers (TBSC0, TBSC1,
TBSC2, and TBSC3)
• TIMB channel registers (TBCH0H:TBCH0L, TBCH1H:TBCH1L,
TBCH2H:TBCH2L, and TBCH3H:TBCH3L)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Timer Interface Module B (TIMB)
Technical Data
239