MC68HC708MP16 Datasheet, PDF(370/398 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC708MP16 Datasheet, PDF (370/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Electrical Specifications

21.6 DC Electrical Characteristics

Table 21-4. DC Electrical Characteristics (VDD = 5.0 Vdc Â± 10%)(1)

Characteristic

Output High Voltage

(ILOAD = â2.0 mA) All I/O Pins

Output Low Voltage

(ILOAD = 1.6mA) All I/O Pins

PWM Pin Output Source Current

(VOH = VDD â0.8 V)

PWM Pin Output Sink Current

(VOL = 0.8 V)

Input High Voltage

All ports, IRQs, RESET, OSC1

Input Low Voltage

All ports, IRQs, RESET, OSC1

Symbol

VOH

Min

VDD â0.8

Typ(2)

â

Max

â

Unit

V

VOL

â

â

0.4

V

IOH

7

â

â

mA

IOL

â20

â

â

mA

VIH

0.7 x VDD

â

VDD

V

VIL

VSS

â

0.3 x VDD V

VDD Supply Current

Run (3)

Wait (4)

Quiescent(5)

I/O Ports Hi-Z Leakage Current

Input Current

Capacitance

Ports (as Input or Output)

Low-Voltage Inhibit Reset

Low-Voltage Reset/Recover Hysteresis

POR ReArm Voltage(6)*

POR Rise Time Ramp Rate(8)

IDD

IIL

IIN

COUT

CIN

VLVR

HLVR

VPOR

RPOR

â

â

â

â

â

â

â

4.33

50

0

0.035

â

â

â

â

â

â

â

4.45

100

â

â

40

mA

14

mA

750

ÂµA

Â± 10

ÂµA

Â±1

ÂµA

12

8

pF

4.58

V

150

mV

100

mV

â

V/m

s

Notes:

1. VDD = 5.0 Vdc Â±Â± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25 Â°C only.

3. Run (operating) IDD measured using external square wave clock source (fosc = 8.2 MHz). All inputs 0.2 V from rail. No

dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance

linearly affects run IDD. Measured with all modules enabled.

4. Wait IDD measured using external square wave clock source (fosc = 8.2 MHz); all inputs 0.2 V from rail; no dc loads;

less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects

wait IDD; measured with PLL, and LVI enabled.

5. Quiescent IDD measured with PLL and LVI disengaged, OCS1 grounded, no port pins sourcing current. Measured

through combination of VDD, VDDAD, and VDDA.

6. Maximum is highest voltage that POR is guaranteed.

7. Maximum is highest voltage that POR is possible.

8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until

minimum VDD is reached.

Technical Data

370

Electrical Specifications

MC68HC708MP16 â Rev. 3.1

Freescale Semiconductor

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