MC68HC708MP16 Datasheet, PDF (166/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
If the FINTx bit is set, a fault condition resulting in setting the
corresponding FFLAG bit will also latch a CPU interrupt request. The
interrupt request latch is not cleared until one of the following actions
occurs:
• The FFLAGx bit is cleared by writing a 1 to the corresponding
FTACKx bit.
• Clearing the FINTx bit. (This will not clear the FFLAGx bit.)
• Reset — A reset automatically clears all four interrupt latches
If prior to a vector fetch, the interrupt request latch is cleared by one of
the above actions, a CPU interrupt will no longer be requested. A vector
fetch does not alter the state of the PWMs, the FFLAGx event flag or
FINTx.
NOTE: If the FFLAGx or FINTx bits are not cleared during the interrupt service
routine, the interrupt request latch will not be cleared.
9.7.1.3 Manual Mode
In manual mode, the PWM(s) are disabled immediately once a filtered
fault condition is detected (logic high). The PWM(s) remain disabled until
software clears the corresponding FFLAGx event bit and a new PWM
cycle begins. In manual mode, the fault pins are grouped in pairs, each
pair sharing common functionality. A fault condition on pins 1 and 3 may
be cleared, allowing the PWM(s) to enable at the start of a PWM cycle
regardless of the logic level at the fault pin. See Figure 9-36. A fault
condition on pins 2 and 4 can only be cleared, allowing the PWM(s) to
enable, if a logic low level at the fault pin is present at the start of a PWM
cycle. See Figure 9-37.
Technical Data
166
MC68HC708MP16 — Rev. 3.1
Pulse Width Modulator for Motor Control (PWMMC) Freescale Semiconductor