MC68HC708MP16 Datasheet, PDF (159/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
the odd OUTx bit toggles as shown in Figure 9-29. Although dead-time
is not inserted when the even OUTx bits change, there will be no dead-
time violation as shown in Figure 9-30.
Setting the OUTCTL bit does not disable the PWM generator and current
sensing circuitry. They continue to run, but are no longer controlling the
output pins. In addition, OUTCTL will control the PWM pins even when
PWMEN = 0. When OUTCTL is cleared, the outputs of the PWM
generator become the inputs to the dead-time and output circuitry at the
beginning of the next PWM cycle.
NOTE:
To avoid an unexpected dead-time occurrence, it is recommended that
the OUTx bits be cleared prior to entering and prior to exiting individual
PWM output control mode.
9.7 Fault Protection
Conditions may arise in the external drive circuitry which require that the
PWM signals become inactive immediately, such as an overcurrent fault
condition. Furthermore, it may be desirable to selectively disable
PWM(s) solely with software.
One or more PWM pins can be disabled (forced to their inactive state)
by applying a logic high to any of the four external fault pins or by writing
a logic high to either of the disable bits (DISX and DISY in PWM control
register 1). Figure 9-31 shows the structure of the PWM disabling
scheme. While the PWM pins are disabled, they are forced to their
inactive state. The PWM generator continues to run — only the output
pins are disabled.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
159