MC68HC708MP16 Datasheet, PDF (278/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (Figure 13-4 and Figure 13-6.) To transmit
data between SPI modules, the SPI modules must have identical
CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 13-4 and Figure 13-6.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. (See Figure 13-12.) Reset sets
the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pull-up devices on pins SPSCK,
MOSI, and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See 13.10 Resetting the SPI.) Reset clears
the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Technical Data
278
Serial Peripheral Interface Module (SPI)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor