MC68HC708MP16 Datasheet, PDF (107/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
Addr.
$FE0B
$FE0C
$FE0D
Name
Bit 7 6
5
4
3
Read:
PLLF
1
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
1
Read:
LOCK
0
PLL Bandwidth Control
Register (PBWC)
Write:
AUTO
ACQ
XLD
Reset: 0
0
0
0
0
Read:
PLL Programming Register
(PPG)
Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
= Unimplemented
Figure 8-2. CGM I/O Register Summary
2
1 Bit 0
1
1
1
1
1
1
0
0
0
0
VRS6
0
VRS5
0
VRS4
1
1
0
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
8.4.2.1 PLL Circuits
The PLL consists of the following circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
107