MC68HC708MP16 Datasheet, PDF (91/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the LVI_TRIPF voltage and remains at or below that
level for at least nine consecutive CPU cycles. The LVI bit in the SIM
reset status register (SRSR) is set, and the external reset pin (RST) is
held low while the SIM counter counts out 4096 CGMXCLK cycles.
Sixty-four CGMXCLK cycles later, the CPU is released from reset to
allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.
7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) to allow
the oscillator time to stabilize before enabling the internal bus (IBUS)
clocks. The SIM counter also serves as a prescaler for the computer
operating properly module (COP). The SIM counter overflow supplies
the clock for the COP module. The SIM counter is 13 bits long and is
clocked by the falling edge of CGMXCLK.
7.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
7.5.2 SIM Counter and Reset States
External reset has no effect on the SIM counter. The SIM counter is free-
running after all reset states. (See 7.4.2 Active Resets from Internal
Sources for counter control and internal reset recovery sequences.)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
91