MC68HC708MP16 Datasheet, PDF (236/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
4. In TIMB channel x status and control register (TBSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB:MSxA. (See Table 12-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 12-2.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H:TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSCR0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIMB channel 2 registers (TBCH2H:TBCH2L)
initially control the PWM output. TIMB status control register 2
(TBSCR2) controls and monitors the PWM signal from the linked
channels. MS2B takes priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Technical Data
236
Timer Interface Module B (TIMB)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor