MC68HC708MP16 Datasheet, PDF (165/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
9.7.1.1 Fault Pin Filter
Each fault pin incorporates a filter to assist in determining a genuine fault
condition. After a fault pin has been logic low for one CPU cycle, a rising
edge (logic high) will be synchronously sampled once per CPU cycle for
two cycles. If both samples are detected logic high, the corresponding
FPIN bit and FFLAG bit will be set. The FPIN bit will remain set until the
corresponding fault pin is logic low and synchronously sampled once in
the following CPU cycle.
9.7.1.2 Automatic Mode
In automatic mode, the PWM(s) are disabled immediately once a filtered
fault condition is detected (logic high). The PWM(s) remain disabled until
the filtered fault condition is cleared (logic low) and a new PWM cycle
begins as shown in Figure 9-35. Clearing the corresponding FFLAGx
event bit will not enable the PWMs in automatic mode.
FILTERED FAULT PIN
PWM(S)
PWM(S) DISABLED (INACTIVE)
PWM(S) ENABLED
Figure 9-35. PWM Disabling in Automatic Mode
The filtered fault pins’ logic state is reflected in the respective FPINx bit.
Any write to this bit is overwritten by the pin state. The FFLAGx event bit
is set with each rising edge of the respective fault pin after filtering has
been applied. To clear the FFLAGx bit, the user must write a 1 to the
corresponding FTACKx bit.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
165