MC68HC708MP16 Datasheet, PDF (269/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
13.9 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 13-2. SPI Interrupts
Flag
SPTE
(Transmitter Empty)
SPRF
(ReceiverFull)
OVRF
(Overflow)
MODF
(Mode Fault)
Request
SPI Transmitter CPU Interrupt Request (DMAS = 0,
SPTIE = 1,SPE = 1)
SPI Receiver CPU Interrupt Request (DMAS = 0, SPRIE = 1)
SPI Receiver/Error Interrupt Request (ERRIE = 1)
SPI Receiver/Error Interrupt Request (ERRIE = 1)
Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. (See Figure 13-11.)
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
269