MC68HC708MP16 Datasheet, PDF (176/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
NOTE: The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM.
A PWM CPU interrupt request can still be generated when LDOK is zero.
ISENS1:ISENS0 — Current Sense Correction Bits
These read/write bits select the top/bottom correction scheme as
shown in Table 9-8.
Table 9-8. Correction Methods
Current Correction Bits
ISENS1:ISENS0
00
01
10
11
Correction Method
Bits IPOL1, IPOL2, and IPOL3 used for correction
Current sensing on pins IS1, IS2, and IS3 occurs
during the dead-time.
Current sensing on pins IS1, IS2, and IS3 occurs
at the half cycle in center-aligned mode and at
the end of the cycle in edge-aligned mode.
PWMF— PWM Reload Flag
This read/write bit is set at the beginning of every reload cycle
regardless of the state of the LDOK bit. This bit is cleared by reading
PWM control register 1 with the PWMF flag set, then writing a logic 0
to PWMF. If another reload occurs before the clearing sequence is
complete, then writing logic 0 to PWMF has no effect.
1 = New reload cycle began
0 = New reload cycle has not begun
NOTE: When PWMF is cleared, pending PWM CPU interrupts are cleared (not
including fault interrupts).
PWMINT — PWM Interrupt Enable
This read/write bit allows the user to enable and disable PWM CPU
interrupts. If set, a CPU interrupt will be pending when the PWMF flag
is set.
1 = Enable PWM CPU interrupts
0 = Disable PWM CPU interrupts
Technical Data
176
MC68HC708MP16 — Rev. 3.1
Pulse Width Modulator for Motor Control (PWMMC) Freescale Semiconductor