MC68HC708MP16 Datasheet, PDF (305/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface Module (SCI)
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the
SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE
bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of ten or eleven logic 1s from the transmit shift register to
the PTF5/TxD pin. If software clears the TE bit, the transmitter
completes any transmission in progress before the PTF5/TxD returns
to the idle condition (logic 1). Clearing and then setting TE during a
transmission queues an idle character to be sent after the character
currently being transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Communications Interface Module (SCI)
Technical Data
305