MC68HC708MP16 Datasheet, PDF (169/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
9.8 Initialization and the PWMEN Bit
For proper operation, all registers should be initialized and the LDOK bit
should be set before enabling the PWM via the PWMEN bit. When the
PWMEN bit is first set, a reload will occur immediately, setting the PWMF
flag and generating an interrupt if PWMINT is set. In addition, in
complementary mode, PWM value registers 1, 3, and 5 will be used for
the first PWM cycle if current sensing is selected.
NOTE:
If the LDOK bit is not set when PWMEN is set after a RESET, the
prescaler and PWM values will be zero, but the modulus will be
unknown. If the LDOK bit is not set after the PWMEN bit has been
cleared then set (without a RESET), the modulus value that was last
loaded will be used.
If the dead-time register (DEADTM) is changed after PWMEN or
OUTCTL is set, an improper dead-time insertion could occur. However,
the dead time can never be shorter than the specified value.
Because of the equals-comparator architecture of this PWM, the
modulus = 0 case is considered illegal. Therefore, the modulus register
is not reset, and a modulus value of zero will result in waveforms
inconsistent with the other modulus waveforms. See 9.11.2 PWM
Counter Modulo Registers.
When PWMEN is set, the PWM pins change from hi-Z to outputs. At this
time, assuming no fault condition is present, the PWM pins will drive
according to the PWM values, polarity, and dead-time. If the prescaler
bits PRSC1:PRSC0 equal 00 (the default condition), the PWM pins will
drive on the next CPU clock cycle, as shown by the timing diagram in
Figure 9-39.
NOTE:
The timing diagram in Figure 9-39 is only applicable when
PRSC1:PRSC0 = 00. If set to any other value, the PWM outputs will
remain in the high-impedance condition for one complete PWM cycle
before being driven.
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
169