MC68HC708MP16 Datasheet, PDF (350/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
18.5 LVI Status Register
The LVI status register (LVISR) flags V_DD voltages below the LVI_TRIPF
level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
LVI_TRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 18-1.)
Reset clears the LVIOUT bit.
Table 18-1. LVIOUT Bit Indication
At Level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD <
LVI_TRIPR
V_DD
For Number of
CGMXCLK Cycles:
ANY
< 32 CGMXCLK cycles
between 32 & 40 CGMXCLK
cycles
> 40 CGMXCLK cycles
ANY
LVIOUT
0
0
0 or 1
1
Previous Value
Technical Data
350
Low-Voltage Inhibit (LVI)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor