MC68HC708MP16 Datasheet, PDF (246/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. (See Table
12-2.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHxB pin. (See Table 12-2.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMB status and control register
(TBSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E, and pin PTEx/TCHxB is available as a general-purpose I/O
pin. Table 12-2 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
NOTE: Before enabling a TIMB channel register for input capture operation,
make sure that the PTE/TCHxB pin is stable for at least two bus clocks.
Technical Data
246
Timer Interface Module B (TIMB)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor