MC68HC708MP16 Datasheet, PDF (152/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Pulse Width Modulator for Motor Control (PWMMC)
9.6.3.1 Manual Correction
The IPOL1–IPOL3 bits select either the odd or the even PWM value
registers to use in the next PWM cycle.
Table 9-5. Top/Bottom Manual Correction
Bit
IPOL1
IPOL2
IPOL3
Logic state
0
1
0
1
0
1
Output control
PMVAL1 controls PWM1/PWM2 pair
PMVAL2 controls PWM1/PWM2 pair
PMVAL3 controls PWM3/PWM4 pair
PMVAL4 controls PWM3/PWM4 pair
PMVAL5 controls PWM5/PWM6 pair
PMVAL6 controls PWM5/PWM6 pair
NOTE:
The IPOLx bits are buffered so that only one PWM register is used per
PWM cycle. If an IPOLx bit changes during a PWM period, the new value
does not take effect until the next PWM period.
The IPOLx bits take effect at the end of each PWM cycle regardless of
the state of the load okay bit, LDOK.
PWM CONTROLLED BY
ODD PWMVAL REGISTER
PWM CONTROLLED BY
EVEN PWMVAL REGISTER
A
B
A/B
DEADTIME
GENERATOR
IPOLx BIT
PWM CYCLE START
D
Q
CLK
TOP PWM
BOTTOM PWM
Figure 9-20. Internal Correction Logic when ISENS[1:0] = 0X
The best time to change from one PWMVAL register to another is just
before the current zero crossing. Figure 9-21 shows motor voltage
waveforms under high current and low current conditions. During a
Technical Data
152
MC68HC708MP16 — Rev. 3.1
Pulse Width Modulator for Motor Control (PWMMC) Freescale Semiconductor