MC68HC708MP16 Datasheet, PDF (279/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
13.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform the
following functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $001C
Read:
Write:
Bit 7
SPRF
6
ERRIE
5
OVRF
4
MODF
3
SPTE
2
MODFEN
1
SPR1
Bit 0
SPR0
Reset: 0
0
0
0
1
0
0
0
= Unimplemented
Figure 13-14. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Serial Peripheral Interface Module (SPI)
Technical Data
279