MC68HC708MP16 Datasheet, PDF (260/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
13.6.3 Transmission Format When CPHA = 1
Figure 13-6 shows an SPI transmission in which CPHA is logic 1. The
figure should not be used as a replacement for data sheet parametric
information. Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave
out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 13.8.2 Mode Fault Error.) When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore the slave
uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in
systems having only one master and only one slave driving the MISO
data line.
Technical Data
260
(FOSRPSRCEFKECRYECNLCEE#)
SPSCK (CPOL = 0)
1
2
3
4
5
6
7
8
SPSCK (CPOL =1)
(FROM MASMTOERS)I
(FROM SLMAIVSEO)
SS (TO SLAVE)
CAPTURE STROBE
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
LSB
LSB
Figure 13-6. Transmission Format (CPHA = 1)
Serial Peripheral Interface Module (SPI)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor