MC68HC708MP16 Datasheet, PDF (364/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
Table 19-2. ADC Clock Divide Ratio
ADIV2 ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
ADC input clock /1
ADC input clock /2
ADC input clock /4
ADC input clock /8
ADC input clock /16
ADICLK — ADC Input Clock Select
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at 1 MHz,
correct operation can be guaranteed. (See 21.11 Analog-to-Digital
Converter (ADC) Characteristics.)
1 = Internal bus clock
0 = External clock (CGMXCLK)
1 MHz = ^{CGMXCLK or Bus Frequency}
ADIV[2:0]
Technical Data
364
Analog-to-Digital Converter (ADC)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor