MC68HC708MP16 Datasheet, PDF (321/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-4 shows the port A I/O logic.
READ DDRA ($0006)
WRITE DDRA ($0006)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAx
READ PTA ($0000)
Figure 15-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-1 summarizes
the operation of the port A pins.
Table 15-1. Port A Pin Functions
DDRA
Bit
0
PTA Bit
X⁽¹⁾
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Accesses
to DDRA
Read/Write
DDRA[7:0]
1
X
Output
DDRA[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Pin
PTA[7:0]
Write
PTA[7:0]⁽³⁾
PTA[7:0]
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
Input/Output (I/O) Ports
Technical Data
321