MC68HC708MP16 Datasheet, PDF (50/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Addr.
Name
Bit 7
$FE00
SIM Break Status Register Read:
(SBSR)
R
See page 99. ^Write:
Note: Writing a logic 0 clears SBSW. Reset:
$FE01
SIM Reset Status Register ^{Read: POR}
(SRSR) Write:
See page 101. _{Reset: 1}
$FE03
SIM Break Flag Control ^Read:
Register (SBFCR) Write:
See page 102. _Reset:
BCFE
0
$FE07
EPROM Control Register ^{Read: 0}
(EPMCR) Write:
See page 56. _{Reset: 0}
$FE0B
PLL Control Register ^Read:
(PCTL) Write:
See page 117. _Reset:
PLLIE
0
$FE0C
PLL Bandwidth Control ^Read:
Register (PBWC) Write:
See page 119. _Reset:
AUTO
0
$FE0D
PLL Programming Register ^Read:
(PPG) Write:
See page 121. _Reset:
MUL7
0
6
5
R
R
PIN COP
0
0
R
R
0
0
0
PLLF
0
PLLON
0
1
LOCK
ACQ
0
MUL6
0
MUL5
1
1
4
R
ILOP
0
R
0
0
BCS
0
XLD
0
MUL4
0
3
R
ILAD
0
R
0
0
1
1
0
0
VRS7
0
2
1 Bit 0
SBSW
R
R
Note
0
0
LVI
0
0
0
0
R
R
R
ELAT
0
1
0
EPGM
0
0
1
1
1
1
1
0
0
0
0
VRS6
0
VRS5
0
VRS4
1
1
0
$FE0F
LVI Status Register ^{Read: LVIOUT 0}
0
0
0
0
0
0
(LVISR) Write:
See page 350. _{Reset: 0}
0
0
0
0
0
0
0
$FFFF
COP Control Register ^Read:
(COPCTL) Write:
See page 336. _Reset:
X = Indeterminate U = Unaffected
Low byte of reset vector
Writing to $FFFF clears COP counter
Unaffected by reset
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
Technical Data
50
Memory Map
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor