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MC68HC708MP16 Datasheet, PDF (372/398 Pages) Freescale Semiconductor, Inc – Microcontrollers
◁
Electrical Specifications
21.8 Serial Peripheral Interface Characteristics
Table 21-6. Serial Peripheral Interface (SPI) Timing (VDD = 5.0 Vdc ± 10%) (1)
Diagram
Number(2)
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
Cycle Time
1
Master
Slave
2
Enable Lead Time
3
Enable Lag Time
Clock (SCK) High Time
4
Master
Slave
Clock (SCK) Low Time
5
Master
Slave
Data Setup Time (Inputs)
6
Master
Slave
fOP(M)
fOP(S)
tCYC(M)
tCYC(S)
tLEAD(S)
tLAG(S)
tSCKH(M)
tSCKH(S)
tSCKL(M)
tSCKL(S)
tSU(M)
tSU(S)
fOP/128
DC
2
1
15
15
100
50
100
50
45
5
fOP/2
fOP
128
—
—
—
—
—
—
—
—
—
MHz
tCYC
ns
ns
ns
ns
ns
Data Hold Time (Inputs)
7
Master
Slave
tH(M)
tH(S)
0
15
—
—
ns
Access Time, Slave(3)
8
CPHA = 0
CHPA = 1
tA(CP0)
0
tA(CP1)
0
40
20
ns
9
Disable Time, Slave(4)
tDIS(S)
—
25
ns
Data Valid Time (After Enable Edge)
10
Master
Slave(5)
tV(M)
tV(S)
—
10
ns
—
40
Notes:
1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI
pins.
2. Numbers refer to dimensions in Figure 21-1 and Figure 21-2.
3. Time to data active from high-impedance state.
4. Hold time to high-impedance state.
5. With 100 pF on all SPI pins.
Technical Data
372
Electrical Specifications
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor
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