MC68HC708MP16 Datasheet, PDF (214/398 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module A (TIMA)
PS[2:0]. (See 11.9.1 TIMA Status and Control Register.) The
minimum TCLK pulse width, TCLK_LMIN or TCLK_HMIN, is:
------------------1-------------------
bus frequency
+
t_SU
The maximum TCLK frequency is:
bus frequency ÷ 2
PTE0/TCLKA is available as a general-purpose I/O pin when not used
as the TIMA clock input. When the PTE0/TCLKA pin is the TIMA clock
input, it is an input regardless of the state of the DDRE0 bit in data
direction register E.
11.8.2 TIMA Channel I/O Pins (PTE1/TCH0A:PTE2/TCH1A)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0A and PTE2/TCH1A
can be configured as buffered output compare or buffered PWM pins.
11.9 I/O Registers
The following I/O registers control and monitor operation of the TIM:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH:TACNTL)
• TIMA counter modulo registers (TAMODH:TAMODL)
• TIMA channel status and control registers (TASC0 and TASC1)
• TIMA channel registers (TACH0H:TACH0L and
TACH1H:TACH1L)
Technical Data
214
Timer Interface Module A (TIMA)
MC68HC708MP16 — Rev. 3.1
Freescale Semiconductor